Analysis and optimization of ground bounce in digital CMOS circuits

Author

Heydari, Payam ; Pedram, Massoud

Author_Institution

Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA

fYear

2000

fDate

2000

Firstpage

121

Lastpage

126

Abstract

This paper is concerned with the analysis and optimization of the ground bounce in digital CMOS circuits. First, an analytical method for calculating the ground bounce is presented. The proposed method relies on accurate models of the short-channel MOS device and the chip-package interface parasitics. Next the effect of ground bounce on the buffer propagation delay and the optimum taper factor is discussed and a mathematical relationship for total propagation delay in the presence of the ground bounce is obtained. The effect of the on-chip decoupling capacitor on ground bounce waveform and the circuit performance is analyzed next and a closed form expression for the peak value of the differential mode component of the ground bounce in terms of on-chip decoupling capacitor is provided. Finally a design methodology for controlling the switching times of the output drivers to minimize the ground bounce is presented

Keywords

CMOS digital integrated circuits; VLSI; circuit analysis computing; buffer propagation delay; chip-package interface parasitics; closed form expression; differential mode component; digital CMOS circuits; ground bounce; on-chip decoupling capacitor; optimum taper factor; short-channel MOS device; total propagation delay; CMOS digital integrated circuits; Circuit analysis; Circuit optimization; Design methodology; MOS capacitors; MOS devices; Performance analysis; Propagation delay; Semiconductor device modeling; Switched capacitor circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design, 2000. Proceedings. 2000 International Conference on

Conference_Location

Austin, TX

ISSN

1063-6404

Print_ISBN

0-7695-0801-4

Type

conf

DOI

10.1109/ICCD.2000.878277

Filename

878277