A parameterizable HandelC divider generator for FPGAs with embedded hardware multipliers

This work presents a parameterizable tool that generates HandelC code to perform fast division on FPGAs. With the introduction of VirtexII family FPGAs, fast division is now achievable by exploiting 18-bit hardware multipliers and fast block RAM (BRAM). Look up tables (LUTs) are used to store reciprocals of the denominators that are used in conjunction with the multiplier. This produces a low latency divider that consumes very little FPGA area, but at the cost of precision. In image processing applications, these properties are ideal.