DocumentCode
2549924
Title
Fast tracker performance using the new “variable resolution associative memory” for ATLAS
Author
Iizawa, Tomoya
Author_Institution
Waseda Univ., Tokyo, Japan
fYear
2012
fDate
Oct. 27 2012-Nov. 3 2012
Firstpage
1392
Lastpage
1395
Abstract
The Fast Tracker (FTK) for the ATLAS trigger is a state-of-the-art online processor that tackles and solves the full track reconstruction problem at a hadron collider. We describe an important advancement for the Associative Memory device (AM). The AM is a VLSI processor for pattern recognition based on Content Addressable Memory (CAM) architecture. Pattern matching is carried out by finding track candidates in coarse resolution "roads". A large AM bank stores all trajectories of interest, called "patterns", for a given detector resolution. The AM extracts roads compatible with a given event at each level-1 read-out. Two important variables characterize the quality of the AM bank: its "coverage" and the level of fake roads. The coverage, which describes the geometric efficiency of a bank, is defined as the probability for a track to match at least one pattern in the bank. To optimize the efficiency the easiest way is to increase the road size, keeping the number of patterns low and the system cheap. But this has a bad performance at high luminosity, where large roads are sensitive to the combinatoric effect, pushing on the contrary to use smaller roads and more patterns and making the system extremely expensive. We propose an elegant solution to this problem: the "variable resolution patterns". Each detector layer within a pattern will be able to use the optimal width. Using a "don\´t care" feature (inspired from ternary CAMs) to increase the width when that is more appropriate. In other words we can use patterns of variable shape. We will show how this reduces the number of fake roads, while keeping the efficiency high and avoiding excessive bank size due to the reduced width.
Keywords
VLSI; nuclear electronics; particle tracks; pattern matching; position sensitive particle detectors; readout electronics; AM bank size; ATLAS trigger; Content Addressable Memory architecture; VLSI processor; combinatoric effect; detector resolution; fast tracker performance; geometric efficiency; hadron collider; pattern matching; pattern recognition; read-out electronics; road size; ternary CAMs; track reconstruction; track reconstruction problem; variable resolution associative memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2012 IEEE
Conference_Location
Anaheim, CA
ISSN
1082-3654
Print_ISBN
978-1-4673-2028-3
Type
conf
DOI
10.1109/NSSMIC.2012.6551339
Filename
6551339
Link To Document