Comparative study of parallel algorithms for 3-D capacitance extraction on distributed memory multiprocessors

Author

Yuan, Yanhong ; Banerjee, Prithviraj

Author_Institution

Dept. of Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA

fYear

2000

fDate

2000

Firstpage

133

Lastpage

138

Abstract

Very fast and accurate 3-D capacitance extraction is essential for ultra deep sub-micron design (UDSM) of integrated circuits. Parallel processing provides an approach to reducing the simulation turn-around time. In this paper, we present two parallel formulations for 3-D capacitance extraction, based on the fast multipole method (FMM) and the direct boundary element method (BEM), respectively. We report detailed comparison results on parallel efficiency and memory scalability, on three different distributed memory platforms, including a 16 processor IBM SP2, and ATM network of 16 HP workstations, and an Ethernet network of 16 HP workstations

Keywords

circuit layout CAD; distributed memory systems; parallel algorithms; 16 processor IBM SP2; 3-D capacitance extraction; ATM network; Ethernet network; HP workstations; direct boundary element method; distributed memory multiprocessors; distributed memory platforms; fast multipole method; memory scalability; parallel algorithms; ultra deep sub-micron design; Capacitance; Circuits; Clustering algorithms; Conductors; Ethernet networks; Parallel algorithms; Parallel processing; Signal design; Supercomputers; Workstations;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer Design, 2000. Proceedings. 2000 International Conference on

Conference_Location

Austin, TX

ISSN

1063-6404

Print_ISBN

0-7695-0801-4

Type

conf

DOI

10.1109/ICCD.2000.878279

Filename

878279