DocumentCode
2550002
Title
Compact implementation of linear weighted CMOS transconductance adder based on the flipped voltage follower
Author
Padilla, Ivan ; Ramirez-Angulo, Jaime ; Carvajal, Ramon G. ; Lopez-Martin, Antonio J. ; Carlosena, Alfonso
Author_Institution
Klipsch Sch. of Electr. & Comput. Eng., New Mexico State Univ., Las Cruces, NM
fYear
2006
fDate
21-24 May 2006
Lastpage
4284
Abstract
A new implementation of a resistorless and capacitorless scheme for continuous time highly linear weighted additions is presented. It is based on a circuit denoted "flipped folded voltage follower". Simulation and experimental results from a test chip prototype in 0.5mum technology validate the proposed circuit
Keywords
CMOS analogue integrated circuits; operational amplifiers; summing circuits; 0.5 micron; CMOS; capacitorless implementation; continuous time; flipped folded voltage follower; flipped voltage follower; linear weighted additions; linear weighted transconductance adder; resistorless implementation; Adders; CMOS technology; Circuit testing; Impedance; MOSFETs; Operational amplifiers; Resistors; Transconductance; Transconductors; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location
Island of Kos
Print_ISBN
0-7803-9389-9
Type
conf
DOI
10.1109/ISCAS.2006.1693575
Filename
1693575
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