DocumentCode :
2550005
Title :
Multilevel reverse-carry adder
Author :
Bruguera, Javier D. ; Lang, Toms
Author_Institution :
Dept. of Electron. & Comput. Eng., Santiago de Compostela Univ., Spain
fYear :
2000
fDate :
2000
Firstpage :
155
Lastpage :
162
Abstract :
The multilevel reverse-carry approach has been proposed previously for fast computation of the most-significant carry of an adder. We extend this approach to generate several carries and apply it to the implementation of the complete adder. Specifically, the operands are split into blocks and each block is added to produce the sum and the sum plus one. Concurrently with these additions the multilevel reverse-carry approach is used to generate the input carries of these blocks. Finally, these carries are used to select among the sum and the sum plus one. We have evaluated the resulting architecture for a 64-bit adder, considering the load introduced by long connections, and we estimate a reduction of about 15% in the critical path delay with respect to traditional implementations of prefix-tree based adders
Keywords :
adders; carry logic; logic design; critical path delay; most-significant carry; multilevel reverse-carry adder; prefix-tree based adders; Adders; Contracts; Delay effects; Delay estimation; Partitioning algorithms; Proposals; Signal generators; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design, 2000. Proceedings. 2000 International Conference on
Conference_Location :
Austin, TX
ISSN :
1063-6404
Print_ISBN :
0-7695-0801-4
Type :
conf
DOI :
10.1109/ICCD.2000.878282
Filename :
878282
Link To Document :
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