Retiming aware clustering for sequential circuits

This work presents a simultaneous sequential retiming and clustering algorithm for delay minimization applicable to FPGAs. The algorithm is based on Pan et al.(1998) with several modifications and enhancements to improve the performance of the final clustered circuits. A duplication control strategy is used to reduce the amount of node duplication. Experimental results on the biggest MCNC benchmark circuits using Altera´s Quartus show that our algorithm can increase the performance, on average, by almost 22% compared with the case when Quartus is used without our clustering information.