Impact of Single Charge Trapping on the Variability of Ultrascaled Planar and Trigate FDSOI MOSFETs: Experiment Versus Simulation

The impact of single charge trapping on the threshold voltage Vt of ultrascaled fully depleted silicon-on-insulator transistors is investigated through dynamic variability measurements and 3-D electrostatic simulations. In these undoped Si channel devices, Vt shifts induced by individual trapping events are exponentially distributed with distribution tail similarly as in BULK devices. This typical dependence is explained by the high sensitivity of Vt -with a bell-like shape-on the position of the trap over the channel. The tail, on the other hand, is attributed to defects in the buried oxide. Finally, device scaling is showed to increase dynamic Vt variability. In particular, the impact of a single charge on Vt is found to scale with the inverse of the device area.