• DocumentCode
    2550309
  • Title

    Architectures for ICT on FPGA

  • Author

    Patino, A.M. ; Peiró, Marcos A Martinez ; Ballester, Francisco ; Payá, G.

  • Author_Institution
    Instituto Tecnologico de Morelia, Mexico
  • fYear
    2004
  • fDate
    6-8 Dec. 2004
  • Firstpage
    403
  • Lastpage
    406
  • Abstract
    We evaluate some architectures for the implementation on FPGA of the one and two dimensions integer cosine transform (ICT). The area and speed synthesis results are shown. The ICT is the transformation used in the newest video compression standard H.264/AVC.
  • Keywords
    data compression; field programmable gate arrays; transforms; video coding; 1D integer cosine transform; 2D integer cosine transform; H. 264/AVC; field programmable gate arrays; video compression; Automatic voltage control; Discrete cosine transforms; Discrete transforms; Equations; Field programmable gate arrays; Hardware; Quadratic programming; Quantization; Roundoff errors; Video compression;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on
  • Print_ISBN
    0-7803-8651-5
  • Type

    conf

  • DOI
    10.1109/FPT.2004.1393310
  • Filename
    1393310
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2550309