Analysis of ternary multiplier using booth encoding technique

This paper introduces a new approach to multiplication of ternary numbers. The whole multiplication is based on the efficient Booth Encoding technique that multiplies both positive as well as negative ternary numbers. Verilog HDL has been used to implement the ternary multipliers of 3bit, 8bit and 12bit. The HDL design is based on the Finite State Machine (FSM) and multiplexing techniques. The design is simulated using ModelSim SE 6.5 and synthesized using Xilinx ISE Design Suite 14.1. The results obtained from the proposed design in terms of delay, power and area have been compared with the conventional multiplier design.