Study on column wise design compaction for reconfigurable systems

Some of currently available field programmable gate arrays (FPGAs) can be reconfigured partially, which makes it possible to build up dynamic systems that can be adapted to changing demands during runtime. One basic aspect of such a system is the way the dynamic hardware modules are placed on the FPGA. As most FPGAs offer partial reconfiguration in a column wise manner, a 1D placement of column wise implemented modules seems to be promising. Within This work we present a design study that determines the effects of a column wise module implementation on the resulting frequency and power consumption.