• DocumentCode
    2550443
  • Title

    Dynamic flip-flop with improved power

  • Author

    Nedovic, Nikola ; Oklobdzija, Vojin G.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    323
  • Lastpage
    326
  • Abstract
    An improved design of a dynamic flip-flop is presented. The proposed design overcomes the problem of the glitch at the output and improves power-delay product for about 27%, while preserving logic embedding property. This is accomplished by equalizing the tpLH and tpHL of the flip-flop and careful design of keeper elements in the circuit. New design introduces insignificant area increase
  • Keywords
    flip-flops; logic design; dynamic flip-flop; keeper elements; logic embedding property; power-delay product; Clocks; Delay; Energy consumption; Flip-flops; Laboratories; Latches; Logic; MOSFETs; Power engineering computing; Topology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design, 2000. Proceedings. 2000 International Conference on
  • Conference_Location
    Austin, TX
  • ISSN
    1063-6404
  • Print_ISBN
    0-7695-0801-4
  • Type

    conf

  • DOI
    10.1109/ICCD.2000.878303
  • Filename
    878303
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2550443