An FPGA implementation of a modified version of RED algorithm

Author

Fereydouni-Forouzandeh, F. ; Mohamed, Otmane Ait

Author_Institution

Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada

fYear

2004

fDate

6-8 Dec. 2004

Firstpage

425

Lastpage

428

Abstract

Receiving large number of data packets at different baud rates and different sizes at gateways in very high-speed network routers may lead to a congestion problem and force them to drop some packets. Several algorithms have been developed to control this problem. A random early detection (RED) algorithm is commonly used. In this work, we present an FPGA implementation of a modified version of RED able to run as fast as 10 Gbps. Furthermore, we discuss three enhancements of the RED algorithm leading a better performance suitable for FPGA implementation.

Keywords

data communication; field programmable gate arrays; telecommunication congestion control; telecommunication network routing; telecommunication traffic; FPGA implementation; RED algorithm; baud rates; data packets; field programmable gate arrays; random early detection; very high-speed network routers; Clocks; Computer hacking; Counting circuits; Field programmable gate arrays; Floating-point arithmetic; Hardware; High-speed networks; Lead compounds; Timing; Traffic control;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on

Print_ISBN

0-7803-8651-5

Type

conf

DOI

10.1109/FPT.2004.1393316

Filename

1393316