An embedded low power reconfigurable fabric for finite state machine operations

Generic reconfigurable finite state machine (FSM) array architecture is presented in this paper. The architecture has been customized for reconfiguration targeting applications requiring large number of states with the added advantage of low power consumption. Examples of up to 256 states have been targeted in this paper. Compared with commercial FPGA devices, the architecture provides the following reductions: up to 89.3% in power consumption, up to 55.2% in area and around 8% in delay time