• DocumentCode
    2550501
  • Title

    Xtensa with user defined DSP coprocessor microarchitectures

  • Author

    Ezer, Gulbin

  • fYear
    2000
  • fDate
    2000
  • Firstpage
    335
  • Lastpage
    342
  • Abstract
    This paper describes the third generation configurable and extensible XtensaTM processor with enhanced DSP functionality targeted to System-On-Chip (SOC) designs. Xtensa III processor family can be configured with an IEEE-compatible floating point unit (FPU) and/or a powerful, energy efficient Vector Integer coprocessor, both implemented using Tensilica Instruction Extension (TIE) language and automatically integrated with the Xtensa base processor core
  • Keywords
    coprocessors; digital signal processing chips; floating point arithmetic; IEEE-compatible floating point unit; Tensilica Instruction Extension language; extensible Xtensa processor; system-on-chip designs; user defined DSP coprocessor microarchitectures; vector integer coprocessor; Application software; Computer architecture; Coprocessors; Costs; Digital signal processing; Hardware; Instruction sets; Microarchitecture; Registers; Signal processing algorithms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Design, 2000. Proceedings. 2000 International Conference on
  • Conference_Location
    Austin, TX
  • ISSN
    1063-6404
  • Print_ISBN
    0-7695-0801-4
  • Type

    conf

  • DOI
    10.1109/ICCD.2000.878305
  • Filename
    878305
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2550501