A new reconfigurable architecture with smart data-transfer subsystems for the intelligent image processing

Author

Kadota, Hiroshi ; Hori, Yoshiaki ; Wakatani, Akiyoshi

Author_Institution

Art & Design, Kyushu Univ., Fukuoka, Japan

fYear

2004

fDate

6-8 Dec. 2004

Firstpage

429

Lastpage

432

Abstract

New reconfigurable accelerator architecture suitable for the intelligent image processing is proposed. Not only reconfigurable processing-unit blocks, but also smart data-transfer subsystems which consist of multistage interconnection networks and special buffers are implemented. The subsystem can supply any combinations of 8 × 8 local image data simultaneously to the arbitrary processing units. The processing-unit block consists of arrays of arithmetic units which can be reconfigured as parallel adders/subtracters or multipliers with various precision. The peak performance of this accelerator is 204BOPS which is sufficient for the wavelet transforms in the real-time intelligent image-processing applications.

Keywords

adders; data communication; digital arithmetic; image processing; multiplying circuits; real-time systems; reconfigurable architectures; 204BOPS; arbitrary processing units; arithmetic units array; intelligent image processing; local image data; multistage interconnection networks; parallel adders/subtracters; parallel multipliers; real-time image-processing; reconfigurable accelerator architecture; reconfigurable processing-unit blocks; smart data-transfer subsystems; wavelet transforms; Accelerator architectures; Arithmetic; Concurrent computing; Discrete transforms; Discrete wavelet transforms; Equations; Image processing; Multiprocessor interconnection networks; Object recognition; Reconfigurable architectures;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on

Print_ISBN

0-7803-8651-5

Type

conf

DOI

10.1109/FPT.2004.1393317

Filename

1393317