FleXilicon: a reconfigurable architecture for multimedia and wireless communications

This paper proposes a new reconfigurable architecture for multimedia and wireless communications. The proposed architecture addresses three critical design issues with the loop level parallelism, wide memory bandwidth, reconfigurable controller, and the support of flexible word-length. Several major functions of multimedia and wireless communication applications were implemented in SystemC to estimate the performance of the proposed architecture. Simulation results indicate that the proposed architecture performs far better than conventional processors