An investigation into the design of high-performance shared buffer architectures based on FPGA technology with embedded memory

Author

O´Kane, Stephen ; Sezer, Sakir

Author_Institution

Queens Univ. Belfast, UK

fYear

2004

fDate

6-8 Dec. 2004

Firstpage

461

Lastpage

464

Abstract

The asynchronous nature of packet based communication demands efficient management of buffer resources at network nodes. Shared buffer architectures consequently become one of the dominating constructs of modern routers and switches. This work investigates new and existing shared buffer architectures that are ideal for emerging FPGA technologies with embedded memory.

Keywords

buffer storage; embedded systems; field programmable gate arrays; logic design; memory architecture; shared memory systems; FPGA technology; buffer resources; embedded memory; field programmable gate arrays; network nodes; packet based communication; shared buffer architectures; Asynchronous transfer mode; Communication switching; Field programmable gate arrays; Packet switching; Quality of service; Resource management; Scalability; Switches; Switching circuits; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Technology, 2004. Proceedings. 2004 IEEE International Conference on

Print_ISBN

0-7803-8651-5

Type

conf

DOI

10.1109/FPT.2004.1393325

Filename

1393325

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2550717