An automatic validation methodology for logic BIST in high performance VLSI design

Signature Based Test Generation continues to grow in importance as VLSI circuits cross and leap beyond the multi-million gate mark. The Logic Built-In Self Test (LBIST) methodology is a signature analyst´s based test generation strategy in wide spread use today. Since the LBIST hardware forms the basis for the generation of test patterns and failure-mode diagnostics, it is paramount that the LBIST test structures conform to LBIST methodology requirements. If the LBIST structures are modeled incorrectly, then pattern mismatches may occur at the tester. This paper describes a set of production level algorithms and procedures used to validate the LBIST structures used in the LBIST methodology. The validation includes the identification and verification of individual components of the LBIST structure. These algorithms are based on the test structure validation processes designed within IBM´s TestBench test generation system