Title :
High Speed Lossless Data Compression Architecture
Author :
Mehboob, Rizwana ; Khan, Shoab A. ; Ahmed, Zaheer
Author_Institution :
Center for Adv. Studies in Eng., Islamabad
Abstract :
This paper presents a novel architecture for hardware implementation of LZ1 lossless data compression algorithm. The architecture is scalable depending upon the requirements of parallel comparisons. Several instances of the design are synthesized on an FPGA for 1 Gbits/sec and higher data rates. With the increase in network traffic, large scale digital data storage/retrieval and the requirement for preserving communication channel bandwidth, data compression is receiving enormous attention. For real time applications, hardware implementation of data compression algorithms seems imperative and the only viable solution
Keywords :
data compression; field programmable gate arrays; 1 Gbit/s; LZ1 lossless data compression; field programmable gate arrays; parallel comparisons; Bandwidth; Communication channels; Data compression; Field programmable gate arrays; Hardware; Information retrieval; Large-scale systems; Memory; Network synthesis; Telecommunication traffic; Data Compression; Hardware Implementation; LZ77 Architecture; Parallel Comparisons;
Conference_Titel :
Multitopic Conference, 2006. INMIC '06. IEEE
Conference_Location :
Islamabad
Print_ISBN :
1-4244-0795-8
Electronic_ISBN :
1-4244-0795-8
DOI :
10.1109/INMIC.2006.358141
