DocumentCode :
2551139
Title :
Static timing analysis with false paths
Author :
Chen, Haizhou ; Lu, Bing ; Du, Ding-Zhu
Author_Institution :
Marvell Semicond. Inc., USA
fYear :
2000
fDate :
2000
Firstpage :
541
Lastpage :
544
Abstract :
Finding the longest path and the worst delay is the most important task in static timing analysis. But in almost every digital circuit, there exists false paths which are logically impossible or designers don´t care about their delays. This paper presents a new method to calculate the worst delay of a circuit with known false paths. When searching for the longest path, it stores delays on nodes conditionally with false paths matched up to the node, thus reduces the number of cache entries and eliminates revisits. This method can be applied to incremental delay calculation with little change. Experiments show that the new method is significantly better than path enumeration without conditional cache
Keywords :
delays; logic design; logic testing; timing; cache entries; false paths; incremental delay calculation; static timing analysis; worst delay; Algorithm design and analysis; Circuit analysis computing; Delay; Digital circuits; Integrated circuit interconnections; Logic circuits; Performance analysis; Pins; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Design, 2000. Proceedings. 2000 International Conference on
Conference_Location :
Austin, TX
ISSN :
1063-6404
Print_ISBN :
0-7695-0801-4
Type :
conf
DOI :
10.1109/ICCD.2000.878336
Filename :
878336
Link To Document :
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