Gate current modeling for MOSFETs

The topic of gate current modeling has been of strong interest in recent years, and with the accelerating pace of device miniaturization it is becoming more and important. We present a survey of tunneling models describing carrier transport through insulating layers for semiconductor device simulation. The crucial topics are particularly discussed, namely, models for the energy distribution function, the transmission coefficient for single and layered dielectrics, defect-assisted tunneling and its relation to dielectric degradation and breakdown, and the influence of quasi-bound states in the inversion layer. The models are compared to measurements.