CMOS implementation of efficient 16-Bit square root carry-select adder

A 16-bit Square Root Carry-Select Adder (SQRT CSA) is implemented and analyzed in this paper. The SQRT CSA is an architecture level modification to reduce area and power dissipation as compared to that of conventional CSA. Conventional CSA with Cin=1 block is replaced with binary-to-excess-1 converter (BEC) in the modified SQRT CSA structure. The architecture of 16-bit CSA is configured into five different stages with progressivley increasing data size. In order to realize 16-bit CSA, the basic building blocks, e.g., XOR gate, AND gate, 2:1 Mux, half adder (HA) and full adder (FA) are implemented using CMOS transmission gate (CMOS TG). The ripple carry adder (RCA) and binary-to-excess converter (BEC) of different bit sizes are also implemented. Transistor level schematics are drawn using Mentor Graphics Design Architect and simulations are carried out using Eldo with TSMC 0.35μm CMOS technology and supply voltage of 3.3 V.