Post linearization of CMOS LNA using double cascade FETs

Author

Huang, Guochi ; Kim, Tae-Sung ; Kim, Byung-Sung ; Yu, Mingyan ; Ye, Yizheng

Author_Institution

Microelectron. Center, Harbin Inst. of Technol.

fYear

2006

fDate

21-24 May 2006

Abstract

A novel linearization method is proposed for CMOS LNA design. The proposed LNA adopts two cascode FETs, one of which operates as a conventional current buffer delivering the fundamental current to the load and the other one works as a nonlinear current sinker absorbing the 3rd-order intermodulation distortion (IMD3) current generated by the common source FET. Both single-ended and differential structures are investigated at 2.14 GHz for WCDMA application. The simulation results shows that the single-ended LNA has an 18dBm IIP3 at 11.8 mW power consumption and the differential one has a 12dBm IIP3 at 24.3 mW power consumption

Keywords

CMOS integrated circuits; UHF amplifiers; UHF integrated circuits; buffer circuits; code division multiple access; differential amplifiers; intermodulation distortion; linearisation techniques; low noise amplifiers; 11.8 mW; 2.14 GHz; 24.3 mW; 3rd-order intermodulation distortion; CMOS LNA design; IMD3 current; WCDMA application; cascode FET; circuit simulation; current buffer; differential structures; double cascade FET; nonlinear current sinker; post linearization; single-ended structures; CMOS technology; Character generation; Energy consumption; FETs; Intermodulation distortion; Linearity; MOSFETs; Microelectronics; Transconductance; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693629

Filename

1693629