A WCDMA/HSDPA baseband processor

In this paper, a baseband processor including whole transceiver system for WCDMA/HSDPA communications is presented. In order to resist the non-ideal effect of the wireless channel, the receiver of the proposed processor consists of a channel estimator for channel estimation and receiver parameters calculation, a carrier frequency synchronization and timing synchronization block for carrier frequency offset and clock offset compensation, moreover, an adaptive equalizer for ISI suppression. In receiver architecture design, we adopt applicable algorithms to design each building blocks, so as to minimize the area complexity and power consumption but still with good performance. After system architecture design and system performance simulation, we do some rough evaluation from system architecture about the area and power consumption of the proposed processor