DocumentCode :
2551554
Title :
Incorporating process induced effects into RC extraction
Author :
Chang, Li-Fu ; Dubey, Abhay ; Chang, Keh-Jeng ; Mathews, Rob ; Wong, Ken
Author_Institution :
Frequency Technol. Inc., San Jose, CA, USA
fYear :
1999
fDate :
7-10 Jan 1999
Firstpage :
12
Lastpage :
17
Abstract :
With the advent of deep-submicron technologies, more and more process-induced effects become first-order influences to the performance of VLSI chips. In this paper we will describe a set of wafer-level electrical measurement methods which we have used to measure process-induced effects for several deep-submicron technologies. Seven important interconnect performance parameters have been identified as a minimum set of parameters needed to accurately accommodate the effects and predict the resistance and capacitance of the state-of-the-art interconnect systems. Therefore, interconnect parasitic estimation, or interchangeably in this paper, RC extraction, has to be improved to incorporate those parameters. It is also essential that process/TCAD describes those parameters in a format that allows more accurate parasitic estimation
Keywords :
VLSI; integrated circuit design; integrated circuit interconnections; integrated circuit reliability; technology CAD (electronics); RC extraction; TCAD; VLSI; deep-submicron technologies; interconnect performance parameters; parasitic estimation; process induced effects; process-induced effects; wafer-level electrical measurement methods; Delay estimation; Dielectric constant; Dielectric losses; Electric resistance; Electric variables measurement; Electrical resistance measurement; Integrated circuit interconnections; Semiconductor device measurement; Testing; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Design, 1999. Proceedings. Twelfth International Conference On
Conference_Location :
Goa
ISSN :
1063-9667
Print_ISBN :
0-7695-0013-7
Type :
conf
DOI :
10.1109/ICVD.1999.745117
Filename :
745117
Link To Document :
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