Assignment and reordering of incompletely specified pattern sequences targetting minimum power dissipation

For a significant number of electronic systems used in safety-critical applications circuit testing is performed periodically. For these systems, power dissipation due to Built-in Self Test (BIST) can represent a significant percentage of the overall power dissipation. One approach to minimize power consumption in these systems consists of test pattern sequence reordering. Moreover a key observation is that test patterns are in general expected to exhibit don´t cares, which can naturally be exploited during test pattern sequence reordering. In this paper we develop an optimization model and describe an efficient algorithm for reordering pattern sequences in the presence of don´t cares. Preliminary experimental results amply confirm that the resulting power savings due to pattern sequence reordering using don´t cares can be significant