Title :
On Embedding Test Sets into Hardware Generated Sequences
Author :
Kavvadias, D. ; Sinitos, S. ; Voyiatzis, I. ; Antonopoulou, H. ; Efstathiou, C.
Author_Institution :
Dept. of Math., Univ. of Patras, Patras, Greece
Abstract :
In this paper a novel algorithm is presented for embedding test sets containing don´t care values into sequences generated by binary counters. Experiments carried out on randomly generated test sets reveal that the proposed scheme results in shorter test sequences compared to randomly filling the don´t care bits with `0´ and `1´ values. Furthermore, comparison with schemes that have been proposed in the open literature for embedding test sets into hardware-generated sequences reveal that the proposed schemes presents comparable results, while in many cases it performs better.
Keywords :
built-in self test; circuit analysis computing; embedded systems; binary counter; don´t care values; embedding test set; hardware generated sequence; Built-in self-test; Circuit faults; Filling; Generators; Hardware; Radiation detectors; System-on-a-chip;
Conference_Titel :
Informatics (PCI), 2010 14th Panhellenic Conference on
Conference_Location :
Tripoli
Print_ISBN :
978-1-4244-7838-5
DOI :
10.1109/PCI.2010.44
