Dark current and noise of 100nm thick silicon on sapphire CMOS lateral PIN photodiodes

We report on dark current measurements from lateral, 100nm thick, PIN photodiodes fabricated in the Peregrine Semiconductor, silicon on sapphire (SOS) CMOS technology. We compare interdigitated photodiode geometries with edgeless structures that do not have active device regions adjacent to LOCOS. We also compare two methods for device design. One employs a polysilicon gate to block the implant in the intrinsic region of the device while the second utilizes a specific mask layer in the technology called an SDBlock mask. Our results suggests that the dark current is primarily a function of the junction width. Furthermore, polysilicon gate devices have lower dark currents than SDBlock structures. Finally, we perform noise measurements and extract flicker noise parameters for the two methods and find that polysilicon gate structures have greater levels of flicker noise than SDblock devices