• DocumentCode
    2551746
  • Title

    Concurrent bit-plane coding architecture for EBCOT in JPEG2000

  • Author

    Chiang, Jen-Shiun ; Hsieh, Chang-Yo ; Liu, Jin-Chan ; Chien, Cheng-Chih

  • Author_Institution
    Dept. of Electr. Eng., Tamkang Univ., Taipei
  • fYear
    2006
  • fDate
    21-24 May 2006
  • Abstract
    This work presents a concurrent bit-plane coding architecture for EBCOT of JPEG2000. The architecture uses two bit-planes at the same time to encode data and this scheme can reduce the requirement of internal memory efficiently. Compared with the conventional approach, our concurrent architecture can save 8K-bit internal memory. In our proposed architecture, it can process data as long as the data of the two bit-planes are available, and at the same time the system can keep reading data from the external memory. This approach can increase the computation efficiency and avoid the waiting time for reading external data. It can also reduce the access times of the internal memory. Compared with the conventional context modeling architecture, the proposed concurrent bit-plane coding architecture can reduce the computation time by more than 50%
  • Keywords
    image coding; parallel architectures; EBCOT; JPEG2000; concurrent bit-plane coding; image compression; Arithmetic; Clocks; Computer architecture; Concurrent computing; Context modeling; Discrete wavelet transforms; Image coding; Propagation losses; Quantization; Transform coding;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
  • Conference_Location
    Island of Kos
  • Print_ISBN
    0-7803-9389-9
  • Type

    conf

  • DOI
    10.1109/ISCAS.2006.1693653
  • Filename
    1693653