• DocumentCode
    2551749
  • Title

    A low-complexity, reduced-power Viterbi Algorithm

  • Author

    Singh, P.K. ; Jayasimha, S.

  • Author_Institution
    Signion Syst. Ltd., Hyderabad, India
  • fYear
    1999
  • fDate
    7-10 Jan 1999
  • Firstpage
    61
  • Lastpage
    66
  • Abstract
    We present two memory-, process- and power-efficient algorithmic transformations for the Viterbi Algorithm (VA). The first performs in-place computations reducing memory required and bit transitions on the data address bus, while the second simplifies the traceback routine of the VA
  • Keywords
    Viterbi decoding; Viterbi algorithm; algorithmic transformation; register exchange method; traceback method; Convolution; Convolutional codes; Decoding; Digital signal processing; Electronic switching systems; GSM; Personal communication networks; Satellites; Switches; Viterbi algorithm;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 1999. Proceedings. Twelfth International Conference On
  • Conference_Location
    Goa
  • ISSN
    1063-9667
  • Print_ISBN
    0-7695-0013-7
  • Type

    conf

  • DOI
    10.1109/ICVD.1999.745125
  • Filename
    745125
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2551749