A novel equaliser architecture with dynamic length optimisation

This paper presents a novel architecture for tap-length optimisation of the linear LMS equaliser. No analysis has previously been carried out to determine any tradeoff that exists in circuit area against power saving achieved. A low-complexity length update algorithm is employed to dynamically adjust and optimise the number of taps in the linear equaliser according to channel conditions. The results show that the chosen algorithm presents minimal overhead and reduces power consumed due to optimisation of the equaliser length. This paper presents the first complete architectural VLSI implementation of the length optimised equaliser and includes a performance study in terms of area and power