Title :
PLL-less clock multiplier with self-adjusting phase symmetry
Author :
Pedroni, Volnei A. ; Pedroni, Ricardo U.
Author_Institution :
Parana Fed. Center of Technol. Educ.
Abstract :
We describe a very simple clock multiplier circuit, capable of multiplying the clock frequency by an integer M and producing an output with a relatively symmetric, self-adjusting phase. The circuit is not PLL- nor DLL-based, and feedback loops are not utilized. However, contrary to PLL or DLL systems, it is intended only for relatively low frequencies generation. Experimental results from a MOSIS chip are included
Keywords :
clocks; multiplying circuits; MOSIS chip; PLL-less clock multiplier; clock frequency; multiplying circuit; self-adjusting phase symmetry; simple clock multiplier circuit; Clocks; Counting circuits; Educational technology; Feedback loop; Flip-flops; Frequency; Local oscillators; Phase locked loops; Signal generators; Switches;
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
DOI :
10.1109/ISCAS.2006.1693668
