DocumentCode
2552309
Title
CMOS technology future
Author
Iwai, Hiroshi
Author_Institution
Frontier Collaborative Res. Center, Tokyo Inst. of Technol., Yokohama, Japan
Volume
1
fYear
2004
fDate
3-5 Nov. 2004
Firstpage
179
Lastpage
182
Abstract
Recently, CMOS downsizing has been accelerated very aggressively in both production and research level, and even transistor operation of a 5 nm gate length p-channel MOSFET was reported in a conference. However, many serious problems are expected for implementing small-geometry MOSFETs into large scale integrated circuits even for 45 nm technology node, and it is questionable whether we can successfully introduce sub-10 nm CMOS LSIs into market or not. In this paper, limitation and its possible causes for the downscaling of CMOS are discussed from many aspects.
Keywords
CMOS integrated circuits; MOSFET; large scale integration; 45 nm; 5 nm; CMOS LSI; CMOS downsizing; CMOS integrated circuits; MOSFET; large scale integrated circuits; Acceleration; CMOS integrated circuits; CMOS technology; Collaboration; Electronic circuits; Humans; Integrated circuit technology; Large scale integration; MOSFET circuits; Production;
fLanguage
English
Publisher
ieee
Conference_Titel
Devices, Circuits and Systems, 2004. Proceedings of the Fifth IEEE International Caracas Conference on
Print_ISBN
0-7803-8777-5
Type
conf
DOI
10.1109/ICCDCS.2004.1393378
Filename
1393378
Link To Document