A high-speed, low-complexity radix-2/sup 4/ FFT processor for MB-OFDM UWB systems

Author

Lee, Jeesung ; Lee, Hanho ; Cho, Sang-in ; Choi, Sang-Sung

Author_Institution

Sch. of Inf. & Commun. Eng., Inha Univ., Incheon

fYear

2006

fDate

21-24 May 2006

Abstract

This paper presents the architecture design of a high-speed, low-complexity 128-point radix-2⁴ FFT processor for ultra-wideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using 2-parallel data-path scheme and single-path delay-feedback (SDF) structure. This paper presents the key ideas applied to the design of high-speed, low-complexity FFT processor, especially that for achieving high throughput rate and reducing hardware complexity. The proposed FFT processor has been designed and implemented with the 0.18-mum CMOS technology in a supply voltage of 1.8 V. The throughput rate of proposed FFT processor is up to 1 Gsample/s while it requires much smaller hardware complexity

Keywords

CMOS integrated circuits; OFDM modulation; digital arithmetic; fast Fourier transforms; high-speed integrated circuits; microprocessor chips; ultra wideband communication; 0.18 micron; 1.8 V; CMOS technology; FFT processor; MB-OFDM UWB systems; SDF structure; data-path scheme; hardware complexity; low-complexity FFT architecture; single-path delay-feedback structure; throughput rate; ultrawideband systems; Computer architecture; Costs; Delay; Hardware; Home automation; OFDM; Physical layer; Sampling methods; Throughput; Ultra wideband technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693684

Filename

1693684