A low power adaptive transmitter architecture for low band UWB applications

Author

Zhang, Xiaodong ; Bayoumi, Magdy A.

Author_Institution

Center for Adv. Comput. Studies, Univ. of Louisiana at Lafayette, LA

fYear

2006

fDate

21-24 May 2006

Lastpage

4730

Abstract

An adaptive CMOS UWB transmitter architecture based on programmable pulse position modulation (PPPM) is proposed. It can operate in high-speed mode and power-saving mode depending on various QoS constrains. When the data rate is the primary concern, the transmitter operates at high-speed mode. When the power consumption becomes the major constrain, the transmitter can switch to power-saving mode. The high frequency 80 MHz clock is generated from a 10 MHz low frequency reference by a DLL-based frequency multiplier. The proposed adaptive UWB transmitter has been designed and simulated by using TSMC 0.18mum CMOS process. Simulation results shows proposed transmitter can provide a flexible knob for cross-layer QoS optimization with low power consumption

Keywords

CMOS integrated circuits; delay lock loops; frequency multipliers; low-power electronics; pulse position modulation; quality of service; radio transmitters; ultra wideband communication; 0.18 micron; 10 MHz; 80 MHz; CMOS process; DLL-based frequency multiplier; QoS constrains; QoS optimization; adaptive CMOS ultrawideband transmitter architecture; delay lock loops; high-speed mode; power-saving mode; programmable pulse position modulation; Application software; Clocks; Computer architecture; Energy consumption; Frequency; Hardware; Power generation; Pulse modulation; Radio transmitters; Space vector pulse width modulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693686

Filename

1693686