DocumentCode
2552522
Title
Improved charge pump for reduced clock feed through and charge sharing suppression
Author
Arshak, Khalil ; Abubaker, Omar ; Jafer, Essa
Author_Institution
Dept. of Electron. & Comput. Eng., Limerick Univ., Ireland
Volume
1
fYear
2004
fDate
3-5 Nov. 2004
Firstpage
192
Lastpage
194
Abstract
The design and simulation of an improved charge pump structure has been proposed in this paper to reduce the phase noise of phase locked loop (PLL). The nonideal effects of the charge pump such as the clock feed through, current mismatch and charge sharing are analyzed. The improved and conventional charge pumps are simulated and compared. The charge pump has been designed using 0.35μm TSMC technology and the simulation results is obtained by SPECTRES software.
Keywords
analogue circuits; circuit noise; circuit simulation; network synthesis; phase locked loops; phase noise; PLL; analog circuit design; charge pump; charge sharing suppression; circuit simulation; clock feed through reduction; current mismatch; phase locked loop; phase noise reduction; Charge pumps; Circuit noise; Circuit simulation; Clocks; Feeds; Phase frequency detector; Phase locked loops; Switches; Voltage control; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
Devices, Circuits and Systems, 2004. Proceedings of the Fifth IEEE International Caracas Conference on
Print_ISBN
0-7803-8777-5
Type
conf
DOI
10.1109/ICCDCS.2004.1393381
Filename
1393381
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