Modeling and simulation of digital recombination network for 2-1-1 cascaded doubled-sampled delta-sigma modulator

Author

Salinas-Cruz, R. ; Espinosa-FIores-V, G.

Author_Institution

Benemerita Univ. Autonoma de Puebla, Mexico

Volume

1

fYear

2004

fDate

3-5 Nov. 2004

Firstpage

195

Lastpage

199

Abstract

A mathematical model of the digital recombination network for 2-1-1 cascaded double-sampled (dS) delta-sigma (ΔΣ) modulator, is presented. The model in the z-domain is used to evaluate the performance of the modulator, when the components mismatches are included. A 2-1-1 dS ΔΣ modulator that operates from a single 2.5-V supply is designed in 0.6-μm CMOS technology. The clock frequency is of 26.4 MHz, making the effective sampling of 52.8 MHz, which results in the required signal bandwidth for asymmetrical digital subscriber line (ADSL) applications of 1.1 MHz. The modulator is evaluated with the mathematical model using MATLAB, and for an oversampling of 24, the modulator achieves a signal-to-noise ratio (SNR) of 88-dB, a signal-to-(noise + distortion) ratio (SNDR) of 84-dB, and a dynamic range (DR) of 91-dB.

Keywords

CMOS digital integrated circuits; cascade networks; circuit simulation; digital subscriber lines; integrated circuit modelling; mathematical analysis; sigma-delta modulation; ΔΣ modulator; 0.6 micron; 1.1 MHz; 2-1-1 cascaded doubled-sampled delta-sigma modulator; 2.5 V; 26.4 MHz; 52.8 MHz; CMOS digital integrated circuits; asymmetrical digital subscriber line; circuit simulation; digital recombination network; integrated circuit modeling; mathematical model; Bandwidth; CMOS technology; Clocks; DSL; Delta modulation; Digital modulation; Frequency; Mathematical model; Sampling methods; Semiconductor device modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

Devices, Circuits and Systems, 2004. Proceedings of the Fifth IEEE International Caracas Conference on

Print_ISBN

0-7803-8777-5

Type

conf

DOI

10.1109/ICCDCS.2004.1393382

Filename

1393382