• DocumentCode
    2552622
  • Title

    Formal verification of a snoop-based cache coherence protocol using symbolic model checking

  • Author

    Srinivasan, Srivatsan ; Chhabra, Parminder Singh ; Jaini, Praveen Kumar ; Aziz, Adnan ; John, Lizy

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
  • fYear
    1999
  • fDate
    7-10 Jan 1999
  • Firstpage
    288
  • Lastpage
    293
  • Abstract
    Formal verification of cache coherence in a multiprocessor environment is essential in ascertaining the validity of a cache coherence protocol. Although a number of cache coherence verification techniques are available, very few authors have reported results on verification of cache coherence protocols using symbolic model checking. In this paper we present the verification of a three state snoop-based cache coherence protocol using model checking in VIS. As symbolic model checking is beset with the state explosion problem, directly verifying the protocol for a large number of processors is infeasible. We have developed a set of modeling strategies that we found useful in verifying cache coherence of two to five processor configurations. In this paper, we report the techniques we adopted in modeling and verifying the protocol
  • Keywords
    cache storage; formal verification; memory protocols; multiprocessing systems; symbol manipulation; VIS; formal verification; model checking; multiprocessor environment; processor configurations; snoop-based cache coherence protocol; state explosion problem; symbolic model checking; Clocks; Coherence; Formal verification; Logic; Protocols; State-space methods; System recovery; Time measurement;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Design, 1999. Proceedings. Twelfth International Conference On
  • Conference_Location
    Goa
  • ISSN
    1063-9667
  • Print_ISBN
    0-7695-0013-7
  • Type

    conf

  • DOI
    10.1109/ICVD.1999.745162
  • Filename
    745162