Folded-current-steering DAC: an approach to low-voltage high-speed high-resolution D/A converters

In this paper, a new topology for CMOS current steering DAC, i.e. folded current-steering structure, suitable for low-voltage applications is presented. Using the folded structure, more voltage headroom is available for the current-source devices increasing the output impedance of the current sources. The DAC linearity is thus improved. Also this novel topology improves the value of PSRR and output voltage swing without SFDR degradation and results in more constant load for current cell. Also a current-steering logic decoder with differential outputs is suggested. Besides, gain boosting is applied to increase the output impedance of current source. These techniques are used to design a 12-bit 200MS/s DAC with 1.5-V power supply and more than 72dB SFDR is achieved in all frequencies. Also Monte-Carlo simulations show that the probability of an SFDR of more than 65dB is more than 90% for an input frequency of 100MHz