A model for the distortion due to switch on-resistance in sample-and-hold circuits

Author

Centurelli, Francesco ; Monsurrò, Pietro ; Trifiletti, Alessandro

Author_Institution

Dipt. di Ingegneria Elettronica, Univ. di Roma "La Sapienza"

fYear

2006

fDate

21-24 May 2006

Abstract

A behavioral model of a sample-and-hold circuit is presented, focused on the distortion due to the nonlinear switch on-resistance. A simplified expression for third-order harmonic distortion has been derived, by using a quadratic MOS model where body effect is neglected, and it has been extended to the case of a transmission gate switch. Both the behavioral model and the distortion estimation have been validated by comparison with Cadence simulations, and very low errors have been obtained over a wide range of circuital and signal parameters

Keywords

MOS analogue integrated circuits; harmonic distortion; integrated circuit modelling; phase shifters; sample and hold circuits; Cadence simulations; nonlinear switch on-resistance; quadratic MOS model; sample-and-hold circuits; third-order harmonic distortion; transmission gate switch; Bandwidth; Delay estimation; Harmonic distortion; MOS capacitors; Nonlinear distortion; Phase distortion; Switched capacitor circuits; Switches; Switching circuits; Threshold voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on

Conference_Location

Island of Kos

Print_ISBN

0-7803-9389-9

Type

conf

DOI

10.1109/ISCAS.2006.1693701

Filename

1693701