An efficient regular matrix inversion circuit architecture for MIMO processing

A novel circuit architecture and algorithm is presented for the efficient implementation of a matrix inversion unit. The division-free algorithm yields a scaled version of the inverse and the scaling factor. Based on the Sherman-Morrison formula, the proposed architecture is characterized by regular, locally-connected arrays of processing units and simple iterative processing. It is especially well-suited for covariance matrices, or any other matrix which can be constructed from rank-one updates of an initial matrix whose inverse is known. While it constitutes an ideal solution for antenna array MMSE (minimum mean-square error) processing, it can also be generalized to many other applications with little effort. Implementation results of a heavily pipelined matrix inverter on a Xilinx Virtex-II FPGA are presented, including cost in logic slices and maximum clock frequency. The cost/complexity of the proposed solution is comparable to, and in many cases better than, known alternatives