Title :
Design and Optimization of 40V, 0.18μm versatile HVL-DMOS device with DOE
Author :
Gouh, Michael Tiong Mee ; Hai, Hu Yong ; Pal, Deb Kumar ; Jian, Liu
Author_Institution :
X-FAB Sarawak Sdn. Bhd., Kuching
Abstract :
In this paper, a 40 V versatile HV LDMOS technology with lower Rdson has been developed in the existing 0.18 mum LV CMOS process. The HV LDMOS are designed by using DOE concept on the simulation results from T-supreme followed by Medici. The process complexity to incorporate the HV kept as simple as possible which does not affect much due to baseline. DOE model are constructed from both the critical layout dimensions and implantation scheme. The optimized condition from DOE model provides good breakdown voltage with low Rdson, the values are BVDSS ~77 V & ~59 V; Rdson mu 84 mOmegamm2 & mu192 mOmegamm2 for n-LDMOS p-LDMOS respectively. Final tuning of the process & layout done by splits to improve the other device parameters such as leakage current, substrate current for better reliability & etc.
Keywords :
CMOS integrated circuits; design of experiments; leakage currents; optimisation; power MOSFET; semiconductor device breakdown; semiconductor device models; semiconductor device reliability; DOE concept; breakdown voltage; critical layout dimension; device parameters; device reliability; high voltage LDMOS device optimisation; implantation scheme; leakage current; n-LDMOS device; p-LDMOS device; size 0.18 mum; substrate current; versatile HVL-DMOS device design; voltage 40 V; CMOS process; CMOS technology; Design optimization; Doping; Integrated circuit technology; Medical simulation; Power system reliability; Silicon; US Department of Energy; Very large scale integration;
Conference_Titel :
Semiconductor Electronics, 2008. ICSE 2008. IEEE International Conference on
Conference_Location :
Johor Bahru
Print_ISBN :
978-1-4244-3873-0
Electronic_ISBN :
978-1-4244-2561-7
DOI :
10.1109/SMELEC.2008.4770265
