Novel fault attack resistant Elliptic Curve processor architecture

Fault attacks on Elliptic Curve Cryptosystems have drawn considerable attention. This paper improves fault attack resistant architecture for Elliptic Curve Cryptosystems proposed by Agustin Dominguez et al. using point validation module. Proposed architecture improves the architecture by adding time shared Point Validation module, Zero-One detector and comparator module. The proposed architecture prevents fault, saves computation time and resists revealing of the secret key information. Proposed architecture is implemented on Xilinx Virtex-6 platform. Area is decreased by 5.61% as we have used time shared point validator unit. Also, power is saved by 18.27%.