DocumentCode :
2552943
Title :
Parallel encoders for low-density parity-check convolutional codes
Author :
Bates, Stephen ; Swamy, Ramkrishna
Author_Institution :
Dept. of Electr. & Comput. Eng., Alberta Univ., Edmonton, Alta.
fYear :
2006
fDate :
21-24 May 2006
Abstract :
Low-density parity-check convolutional codes combine the good bit error rate performance of low-density parity-check block codes with the ability to encode and decode arbitrary lengths of data. This makes them attractive in applications where the data unit to be encoded varies in length. In this paper we discuss the parallelization of encoders for low-density parity-check convolutional code. We then present results to show how this parallelism impacts on the area and throughput of VLSI implementations of these encoders. We show how this technique can be used to implement encoders with throughputs suitable for next-generation communication standards and other high-speed applications
Keywords :
VLSI; block codes; convolutional codes; encoding; parallel processing; parity check codes; VLSI implementation; low-density parity-check block code; parallel encoder; parity-check convolutional codes; AWGN; Bit error rate; Block codes; Communication standards; Convolutional codes; Decoding; Field programmable gate arrays; Parallel processing; Parity check codes; Throughput;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Conference_Location :
Island of Kos
Print_ISBN :
0-7803-9389-9
Type :
conf
DOI :
10.1109/ISCAS.2006.1693711
Filename :
1693711
Link To Document :
بازگشت