DocumentCode :
2552966
Title :
Latch-up at RAM control circuitry
Author :
Chiang, Chua Yong
Author_Institution :
Intel Technol., Malaysia
fYear :
1997
fDate :
21-25 Jul 1997
Firstpage :
250
Lastpage :
253
Abstract :
Typically, latch-up is associated with higher input voltage at port pins as compared to power pins, Vcc, causing damage to the protection circuitry or input buffer circuitry. However, for one of the products that is manufactured in Intel, Penang, there have been a number of line yield losses due to latch-up at the RAM control circuitry which happened during burn-in. In this study we have shown the latch-up failures that occasionally caused some yield loss are related to the noise that is generated during high speed switching of transistors in the RAM. We have established the failure mechanism and root cause of the latch-up through layout, schematic and device physics analysis. Implementation of a lower burn-in frequency managed to eliminate the failure mode
Keywords :
failure analysis; integrated circuit reliability; integrated circuit yield; integrated memory circuits; random-access storage; Intel; RAM control circuitry latchup; burn-in; failure mechanism; high speed switching; input buffer circuitry; latch-up failures; noise; protection circuitry; yield losses; Bipolar transistors; Circuit noise; Diodes; Failure analysis; Inverters; Manufacturing; Pins; Protection; Scanning electron microscopy; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Physical & Failure Analysis of Integrated Circuits, 1997., Proceedings of the 1997 6th International Symposium on
Print_ISBN :
0-7803-3985-1
Type :
conf
DOI :
10.1109/IPFA.1997.638329
Filename :
638329
Link To Document :
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