Title :
Improving area efficiency of residue number system based implementation of DSP algorithms
Author :
Mahesh, M.N. ; Gupta, Satrajit ; Mehendale, Mahesh
Author_Institution :
Dept. of Electr. Commun. Eng., Indian Inst. of Sci., Bangalore, India
Abstract :
Residue Number System based applications involve modulo-arithmetic which is typically implemented using look-up-tables (LUTs) for a small value of modulus. In this paper we present a data coding technique to minimize the area of these LUTs when implemented using two level logic structures such as PLAs. We also present a technique that exploits the symmetry in these computations to further optimize the LUTs. Results show that area improvement of upto 66% can be achieved using these techniques
Keywords :
FIR filters; VLSI; digital filters; logic CAD; minimisation of switching nets; programmable logic arrays; residue codes; residue number systems; state assignment; table lookup; DSP algorithms; PLA based implementation; RNS based implementation; area efficiency; data coding technique; inherent symmetry; look-up-tables; modulo-arithmetic; redundancy detection; residue encoding; truth table; two level logic structures; Arithmetic; Concurrent computing; Digital signal processing; Dynamic range; Instruments; Programmable logic arrays; Signal processing; Signal processing algorithms; Table lookup;
Conference_Titel :
VLSI Design, 1999. Proceedings. Twelfth International Conference On
Conference_Location :
Goa
Print_ISBN :
0-7695-0013-7
DOI :
10.1109/ICVD.1999.745179
