CNTFET-based design of dynamic ternary full adder cell

This paper proposes a novel CNTFET-based design of ternary full adder (TFA) cell using dynamic logic style. The proposed TFA is designed based on the conventional CMOS architecture with utilization of inherent binary nature (0, 1) of input carry signal. Since voltage at the output of the dynamic circuit is stored on a parasitic capacitance, a ternary keeper is used in order to alleviate charge sharing problems. The proposed TFA cell is evaluated using HSPICE simulator with 32nm Stanford CNTFET model in various test conditions and at different power supply voltages. The proposed design with output buffer achieves significant improvements in terms of speed, power dissipation and driving capability with respect to other state-of-the-art TFA cells. At 0.9 V, the proposed TFA cell shows 78% reduction in power delay product in comparison to a CNTFET based TFA cell, recently proposed in the literature.