Design and implementation of SET-CMOS hybrid half subtractor

Author

Ghosh, A. ; Jain, A. ; Singh, N.B. ; Sarkar, S.K.

Author_Institution

Dept. of ECE, RCCIIT, Kolkata, India

fYear

2014

fDate

11-13 Dec. 2014

Firstpage

1

Lastpage

4

Abstract

A hybrid SET-CMOS based half subtractor is presented in this paper. Combination of CMOS and SET technology facilitates new advantageous functionalities. The proposed hybrid SET-CMOS based half subtractor is implemented and simulated using T-SPICE. The simulation results are successfully verified with the truth table for the half subtractor. Two different approaches of SET-CMOS hybrid design is explained in this paper. Two main parts of the circuit is formed with the Single electron transistor based network and MOS transistor based network. The circuit of the half subtractor designed using both the approaches is presented in this paper. The stability analysis of the designed circuit is also explained in this paper with the stability plot. Also a performance comparison is given to justify the proposed work.

Keywords

CMOS integrated circuits; MOSFET; SPICE; circuit stability; single electron transistors; MOS transistor based network; T-SPICE; hybrid SET-CMOS based half subtractor; single electron transistor based network; stability analysis; CMOS integrated circuits; Integrated circuit modeling; Logic gates; Mathematical model; Semiconductor device modeling; Single electron transistors; Stability analysis; MIB model; Single electron transistor; half subtractor; hybrid SET-CMOS; power consumption;

fLanguage

English

Publisher

ieee

Conference_Titel

India Conference (INDICON), 2014 Annual IEEE

Conference_Location

Pune

Print_ISBN

978-1-4799-5362-2

Type

conf

DOI

10.1109/INDICON.2014.7030405

Filename

7030405