A fully synthesizable single-precision, floating-point adder/substractor and multiplier in VHDL for general and educational use

Author

Marcus, Guillermo ; Hinojosa, Patricia ; Avila, Alfonso ; Nolazco-FIores, J.

Author_Institution

Instituto Tecnologico y de Estudios Superiores de Monterrey, Mexico

Volume

1

fYear

2004

fDate

3-5 Nov. 2004

Firstpage

319

Lastpage

323

Abstract

We present an adder/substractor and a multiplier for single precision floating point numbers in IEEE-754 format. They are fully synthesizable hardware descriptions in VHDL that are available for general and educational use. Each one is presented in a single cycle and pipelined implementation, suitable for high speed computing, with performance comparable to other available implementations. Precision for non-denormal multiplications is under ulp and for additions in ±1 LSB.

Keywords

IEEE standards; educational computing; floating point arithmetic; hardware description languages; pipeline arithmetic; IEEE-754; LSB; VHDL; floating-point adder; floating-point multiplier; floating-point substractor; high speed computing; nondenormal multiplication; single precision floating point number; synthesizable hardware descriptions; Adders; Circuits; Design methodology; Field programmable gate arrays; Hardware design languages; High performance computing; Microprocessors; Page description languages; Programmable logic arrays; Programming profession;

fLanguage

English

Publisher

ieee

Conference_Titel

Devices, Circuits and Systems, 2004. Proceedings of the Fifth IEEE International Caracas Conference on

Print_ISBN

0-7803-8777-5

Type

conf

DOI

10.1109/ICCDCS.2004.1393405

Filename

1393405